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Server : Apache/2.4.18 (Ubuntu) System : Linux canvaswebdesign 3.13.0-71-generic #114-Ubuntu SMP Tue Dec 1 02:34:22 UTC 2015 x86_64 User : oppastar ( 1041) PHP Version : 7.0.33-0ubuntu0.16.04.15 Disable Function : pcntl_alarm,pcntl_fork,pcntl_waitpid,pcntl_wait,pcntl_wifexited,pcntl_wifstopped,pcntl_wifsignaled,pcntl_wifcontinued,pcntl_wexitstatus,pcntl_wtermsig,pcntl_wstopsig,pcntl_signal,pcntl_signal_dispatch,pcntl_get_last_error,pcntl_strerror,pcntl_sigprocmask,pcntl_sigwaitinfo,pcntl_sigtimedwait,pcntl_exec,pcntl_getpriority,pcntl_setpriority, Directory : /lib/modules/4.4.0-51-generic/build/arch/blackfin/mach-bf518/include/mach/ |
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/* * BF51x memory map * * Copyright 2004-2009 Analog Devices Inc. * Licensed under the GPL-2 or later. */ #ifndef __BFIN_MACH_MEM_MAP_H__ #define __BFIN_MACH_MEM_MAP_H__ #ifndef __BFIN_MEM_MAP_H__ # error "do not include mach/mem_map.h directly -- use asm/mem_map.h" #endif /* Async Memory Banks */ #define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */ #define ASYNC_BANK3_SIZE 0x00100000 /* 1M */ #define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */ #define ASYNC_BANK2_SIZE 0x00100000 /* 1M */ #define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */ #define ASYNC_BANK1_SIZE 0x00100000 /* 1M */ #define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ #define ASYNC_BANK0_SIZE 0x00100000 /* 1M */ /* Boot ROM Memory */ #define BOOT_ROM_START 0xEF000000 #define BOOT_ROM_LENGTH 0x8000 /* Level 1 Memory */ /* Memory Map for ADSP-BF518/6/4/2 processors */ #ifdef CONFIG_BFIN_ICACHE #define BFIN_ICACHESIZE (16 * 1024) #else #define BFIN_ICACHESIZE (0) #endif #define L1_CODE_START 0xFFA00000 #define L1_DATA_A_START 0xFF800000 #define L1_DATA_B_START 0xFF900000 #define L1_CODE_LENGTH 0x8000 #ifdef CONFIG_BFIN_DCACHE #ifdef CONFIG_BFIN_DCACHE_BANKA #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH 0x8000 #define BFIN_DCACHESIZE (16 * 1024) #define BFIN_DSUPBANKS 1 #else #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH (0x8000 - 0x4000) #define L1_DATA_B_LENGTH (0x8000 - 0x4000) #define BFIN_DCACHESIZE (32 * 1024) #define BFIN_DSUPBANKS 2 #endif #else #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) #define L1_DATA_A_LENGTH 0x8000 #define L1_DATA_B_LENGTH 0x8000 #define BFIN_DCACHESIZE 0 #define BFIN_DSUPBANKS 0 #endif /*CONFIG_BFIN_DCACHE */ #endif