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Server : Apache/2.4.18 (Ubuntu) System : Linux canvaswebdesign 3.13.0-71-generic #114-Ubuntu SMP Tue Dec 1 02:34:22 UTC 2015 x86_64 User : oppastar ( 1041) PHP Version : 7.0.33-0ubuntu0.16.04.15 Disable Function : pcntl_alarm,pcntl_fork,pcntl_waitpid,pcntl_wait,pcntl_wifexited,pcntl_wifstopped,pcntl_wifsignaled,pcntl_wifcontinued,pcntl_wexitstatus,pcntl_wtermsig,pcntl_wstopsig,pcntl_signal,pcntl_signal_dispatch,pcntl_get_last_error,pcntl_strerror,pcntl_sigprocmask,pcntl_sigwaitinfo,pcntl_sigtimedwait,pcntl_exec,pcntl_getpriority,pcntl_setpriority, Directory : /usr/src/linux-headers-4.4.0-184/arch/tile/include/uapi/asm/ |
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/* * Copyright 2011 Tilera Corporation. All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation, version 2. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or * NON INFRINGEMENT. See the GNU General Public License for * more details. */ #ifndef _ASM_TILE_CACHECTL_H #define _ASM_TILE_CACHECTL_H /* * Options for cacheflush system call. * * The ICACHE flush is performed on all cores currently running the * current process's address space. The intent is for user * applications to be able to modify code, invoke the system call, * then allow arbitrary other threads in the same address space to see * the newly-modified code. Passing a length of CHIP_L1I_CACHE_SIZE() * or more invalidates the entire icache on all cores in the address * spaces. (Note: currently this option invalidates the entire icache * regardless of the requested address and length, but we may choose * to honor the arguments at some point.) * * Flush and invalidation of memory can normally be performed with the * __insn_flush() and __insn_finv() instructions from userspace. * The DCACHE option to the system call allows userspace * to flush the entire L1+L2 data cache from the core. In this case, * the address and length arguments are not used. The DCACHE flush is * restricted to the current core, not all cores in the address space. */ #define ICACHE (1<<0) /* invalidate L1 instruction cache */ #define DCACHE (1<<1) /* flush and invalidate data cache */ #define BCACHE (ICACHE|DCACHE) /* flush both caches */ #endif /* _ASM_TILE_CACHECTL_H */